1. Field of the Invention
This invention relates to a Quad Flat Non-Lead package of semiconductor, and more particularly to a Quad Flat Non-Lead package of semiconductor that can share an universal lead frame to fit various sizes of chip.
2. Description of Related Art
Following the evolution of the integrated circuit technology, the manufacturing process of integrated circuit has been advanced to ever high in integration with a target of pursuing ever dense package structure in the packaging process of the back end process. The chip scale package (CSP), which has been actively developed and manufactured by the semiconductor industry, has its package size slightly larger than the size of the chip. Therefore, the chip scale package not only can diminish its occupied volume, but also can shorten the path of signal transmission, thereby, it can enhance the product's performance. The carrier employed by the chip scale package includes lead frame, flexible substrate, and rigid substrate etc. The lead-frame-based chip scale package has become a popular consumer electronic product since the lead frame it employed is low in cost and high in workability, thereby, the lead-frame-based chip scale package has become a popular chip scale package.
FIG. 1 is a cross-sectional view of a Quad Flat Non-Lead package of a semiconductor according to the prior art. FIG. 2 is a bottom view corresponding to FIG. 1 according to the prior art. As shown in FIG. 1 and FIG. 2, the structure of the Quad Flat Non-Lead package which has disclosed in the U.S. Pat. No. 5,942,794 (Matsushita, 1999) is constructed on a lead frame and is having a die pad 100 surrounded by a multiple leads 102. The chip 104 includes an active surface 106 and a back surface 108. And a plurality of bonding pads 110 for external connections of the chip 104 is disposed on the active surface 106. The chip 104 has its back surface 108 bonded to the die pad 100 by the use of an adhesive 112 while the bonding pads 110 are electrically connected to the leads 102 respectively by the use of bonding wires 114. What is more, a molding compound 116 normally encapsulates the whole chip 104, the die pad 100, the bonding wires 114, and the top surface 118a of the lead 102. This encapsulating process exposes the bottom surface 118b and the side surface 118c of the leads 102 for external connections of the whole package structure 120.
In the conventional structure of the Quad Flat Non-Lead package, the die pad 100 is upward offset in order to make the chip 104 and leads 102 positioned at different levels of surface. An object of the upward offset of the die pad 100 is that the package can be applied in a relatively large chip in order to make it relatively more flexible in its range of application. The other object is to increase the bondability between the molding compound 116 and the lead frame. However, because of the demand for diminishing the thickness of the package, this conventional package structure is apt to expose the bonding wire 114 while encapsulating, thereby, the yield of the product become lower. Additionally, as the operating speed of the device of the integrated circuit becomes faster and faster nowadays, the heat generated increases accordingly, and since the conventional package structure is unable to provide a better way of heat dissipation, the performance of the electronic device will be affected.
FIG. 3 is a cross-sectional view of another kind of Quad Flat Non-Lead package of a semiconductor according to the prior art and FIG. 4 is a bottom view corresponding to FIG. 3 according to the prior art. As shown in FIG. 3 and FIG. 4, this type of package was presented in a paper titled as "Micro Lead Frame Package" by Amkor Company. The package is constructed on a lead frame that includes a die pad 200 which has a plurality of leads 202 surrounding the die pad 200. The chip 204 has an active surface 206 and a back surface 208. On the active surface 206, there is a plurality of bonding pads 210 for external connections. The back surface 208 of the chip 204 is bonded to the top surface 222a of the die pad 200 by an adhesive 212 while the bonding pads 210 are electrically connected to the top surface 218a of the leads 202 respectively by the bonding wire 214. A molding compound 216 encapsulates the whole chip 204, the bonding wires 214, and the top surface 218a of the lead 202 while exposes the bottom surface 218b and the side surface 218c of the lead 202 for external connections. In additions, the die pad 200 is generally grounded through a bonding wire 214a in order to improve the electrical performance by reducing interference.
Unlike the conventional Quad Flat Non-Lead package shown in FIG. 1, the feature of this kind of conventional Quad Flat Non-Lead package is that the die pad 200 is not upward offset but is exposed in order to enhance the heat-dissipating effect. Despite that this kind of package structure can improve the heat-dissipating effect, it has a disadvantage. In order to accommodate different sizes of the chip 204, the dimension of the die pad 200 and the disposition of the leads 202 need to be adjusted and modified all over. This is because that the die pad 200 is positioned at the same level as the leads 202, and the size of the die pad 200 is slightly greater than the size of the chip 204. Accordingly, the stamping tool employed in the lead frame fabrication process needs to be changed that will increase the manufacturing cost.
In additions, since both the above-mentioned two kinds of Quad Flat Non-Lead package employ half-mold in the encapsulating process, it can not provide appropriate fixture for the die pad and the lead, as a result, the surfaces intended to expose has a flash 224 generated as shown in FIG. 4. Consequently, an extra step is necessary to remove the flash 224 by grinding lest it will affect the package reliability in the subsequent surface mount technology (SMT) process, thereby, it will increase the manufacturing cost.